Si tunneling transistors with high on-currents and slopes of 50 mV/dec using segregation doped NiSi2 tunnel junctions

Planar and nanowire (NW) tunneling field effect transistors (TFETs) have been fabricated on ultra thin strained and unstrained SOI with shallow doped nickel disilicide (NiSi2) source and drain (S/D) contacts. We developed a novel, self-aligned process to form the p-i-n TFETs which greatly simplifies their fabrication by tilted dopant implantation using the high-k/metal gate as a shadow mask and dopant segregation. Two methods of dopant segregation are compared: dopant segregation based on the “snow-plough” effect of dopants during silicidation and implantation into the silicide (IIS) followed by thermal outdiffusion. High drive currents of up to 60 μA/μm of planar p-TFETs were achieved indicating good silicide/silicon tunneling junctions. The non-linear temperature dependence of the inverse subthreshold slope S indicates characteristic TFET behavior. Strained Si NW array n-TFETs with omega shaped HfO2/TiN gates show high drive currents of 7 μA/μm @ 1 V Vdd and steep inverse subthreshold slopes with minimum values of <50 mV/dec due to the smaller band gap of strained Si and optimized electrostatics.

► N- and p- type nanowire-TFETs with high on-currents are fabricated on 6 nm strained SOI. ► Low subthreshold slopes of < 50 mV/dec for n-type TFETs over 3 decades are shown. ► Implementation of epitaxial NiSi2 provides controllable silicide/channel alignment. ► Steep dopant profiles for tunneling junctions were created by implantation into silicide. ► Simple process for p-i-n TFET structure was developed using tilted implantation.