Capacitance–voltage characteristics and device simulation of bias temperature stressed a-Si:H TFTs

In this paper, the degradation of hydrogenated amorphous silicon thin film transistors under a self-heating stress (SHS) condition is investigated by analyzing the capacitance–voltage characteristics of gate-to-drain capacitance (Cgd) and gate-to-source capacitance (Cgs). The very different characteristics of Cgd–Vg and Cgs–Vg show different stress-induced density of states (DOS) property at the drain side and source side of channel. In a long channel device, the Cgd and Cgs characteristics could be explained by the deep states profile which corresponds to the non-uniform threshold voltage profile induced by the bias temperature stress only. The capacitance-voltage and current-voltage curves, simulated using the ATLAS 2D simulator based on the non-uniform defect states profile, agreed well with the measured data. In a short channel device, the simulation fitting of the Cgd and Cgs data required a non-uniform defect states profile, which is substantially modified from the long channel profile. This was interpreted in terms of a significant contribution of the non-uniform temperature distribution, caused by stress-induced self-heating effect in the short channel device, to the defect states density profile in the channel. A decreased density of conduction band tail states at the source end, corresponding to the increased deep Gaussian states, enabled a good simulation fit in the short channel device.