Towards on-chip clocking of perpendicular Nanomagnetic Logic

Perpendicular Nanomagnetic Logic (pNML) is a computing concept, where the local magnetization and fringing fields of ferromagnets are used to store and process information. Most commonly, pNML devices have been operated at millisecond time scales. In this work, pNML magnets are clocked by a planar on-chip inductor at frequencies ranging from 100 kHz to 40 MHz. The inherent switching field (SF) and SF distribution (SFD) of an individual magnet is determined. An Arrhenius equation is used in order to model the SFD especially suited for compact modeling of the NML devices. Furthermore, a magnetic power-clock, implemented by an on-chip inductor with ferromagnetic cladding, is proposed and analyzed by finite element simulations. Clocking frequencies up to 100 MHz at low power are within reach. An estimate of the power density of a scaled pNML computing system extracted from the data is given. The power efficiency of the on-chip field-clock is calculated to be 17%, remarkable for a current-driven clocking concept.