Low-voltage scaling limitations for nano-scale CMOS LSIs

The minimum operating voltage (Vmin) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The Vmin, which is governed by SRAM cells, rapidly increases as devices are miniaturized due to the ever-larger variations in the threshold voltage (VT) of MOSFETs. The Vmin, however, is reduced to the sub-1-V region by using repair techniques and new MOSFETs (e.g., FD-SOIs and/or high-k metal gates) that can reduce VT variations.