Hot-carrier effects as a function of silicon film thickness in nanometer-scale SOI pMOSFETs

The dependence of hot-carrier effects on silicon film thickness is investigated in nanometer-scale SOI pMOSFETs. The results of device simulation and experimental measurements shine light on controversial issues regarding the dependence of hot-carrier effects on the silicon film thickness. For a structure with raised source and drain, it is observed that the peak electric field near drain junction and the gate current increase as the silicon film thickness decreases, and thus that hot-carrier effect are increased. Therefore, hot-carrier induced device degradation in nanometer-scale MuGFETs with elevated source/drain structure should be seriously considered in device design and fabrication. The dependence of hot-carrier effects on silicon film thickness under different stress conditions involving the action of substrate bias and temperature are also discussed.