Achieving low sub-0.6-nm EOT in gate-first n-MOSFET with TiLaO/CeO2 gate stack

We report a gate-first TiLaO/CeO2n-MOSFET with an equivalent oxide thickness (EOT) of only 0.56 nm and threshold voltage (Vt) of 0.31 V. This small EOT MOSFET was achieved by employing high-κ CeO2 interfacial layer with high bond enthalpy (795 kJ/mol) to replace low-κ SiO2 with close bond enthalpy (800 kJ/mol). The cerium silicate can aggressively scale EOT down to sub-0.6-nm EOT region without increasing gate leakage, which is urgently needed for 16 nm technology node.

► Gate-first TiLaO/CeO2n-MOSFET shows an equivalent oxide thickness (EOT) of 0.56 nm and Vt of 0.31 V. ► Cerium silicate interface can aggressively scale EOT down to sub-0.6-nm EOT region. ► Self-aligned and gate-first n-MOSFET with a highly scaled EOT is compatible with CMOS process.