Electrical instability in self-aligned p-channel polysilicon TFTs related to damaged regions present at the gate edges

In this work we present a study of the electrical stability of self-aligned p-channel TFTs fabricated using excimer laser annealing. The electrical stability was tested performing bias stress experiments and accelerated stability tests and we found that the device characteristics were seriously degraded upon application of large negative gate bias. From extensive analysis of the phenomenon through numerical simulations, we found that the device degradation could be perfectly reproduced by positive charge injection into the gate oxide in narrow (300-400 nm) regions at the edges of the gate, near the source and drain contacts. From the present results we conclude that the observed degradation is closely related to the residual damage, induced by ion implantation, present in the gate oxide near the gate edges.