Article ID Journal Published Year Pages File Type
748385 Solid-State Electronics 2008 6 Pages PDF
Abstract

The series resistance at source and drain junctions is evaluated using a surface potential based current vs. gate bias (I–VG) model. To achieve ultimate accuracy and efficiency, a I0–VG model is newly advised for spreadsheet analysis. The electric field dependent mobility model in the literature is modified for easier graphical comparison with the conventional VT-based expression. Using NMOSFETs with different gate length, the exponent for the surface phonon scattering is evaluated to be ≈0.61 for the electric field based expression, and is close to unity in case of the VT-based expression. A smoothly non-linear series resistance vs. gate length relation is successfully confirmed, and the rough agreement with the conventional analysis is discussed to be reasonable.

Related Topics
Physical Sciences and Engineering Engineering Electrical and Electronic Engineering
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