Determining weak Fermi-level pinning in MOS devices by conductance and capacitance analysis and application to GaAs MOS devices

A straightforward methodology is presented to distinguish the presence of large amounts of interface traps causing weak Fermi-level pinning from other effects in MOS capacitors based on GaAs or other alternative semiconductors. This is done by using a simple extraction of a characteristic time constant. The observations for GaAs MOS capacitors are similar to those for Ge MOS capacitors. GaAs MOS capacitors using Ga2O3 and Al2O3 as gate dielectric were investigated and based on this methodology weak Fermi-level pinning due to interface traps was concluded for these devices.