| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 748426 | Solid-State Electronics | 2013 | 4 Pages |
A prospective study of the junctionless transistors (JLTs) scaling performances based both on TCAD and analytical evaluations of the intrinsic delay after considering on/off voltage constraints is proposed. The tradeoffs between speed and switching power performances in regard to the JLT parameters are analyzed. It is demonstrated that JLTs performances in terms of speed are very similar to that of regular bulk MOSFETs, and that increasing the drive current and speed still needs to shrink the gate oxide just as in MOSFETs.
► We propose a prospective study of the junctionless transistors (JLTs) scaling performances. ► Analytical evaluation of the JLT intrinsic delay, after considering on/off voltage constraints, is developed. ► The tradeoffs between speed and switching power performances in regard to the JLT parameters are analyzed. ► It is demonstrated that JLTs performances in terms of speed are very similar to that of regular bulk MOSFETs. ► It is shown that increasing the drive current and speed still needs to shrink the gate oxide just as in MOSFETs.
