| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 748507 | Solid-State Electronics | 2011 | 7 Pages |
Abstract
A three-dimensional (3D) stacked bit-line NAND flash memory is investigated. The fabrication process flow for the formation of a laterally-recessed bit-line stack is described. Program operation is simulated using a stacked bit-line structure. Inter-layer interference (ILI) is addressed and the minimum isolation oxide thickness between stacked bit-lines is extracted. Simple device and array with the laterally-recessed bit-line stack are fabricated and electrical characteristics are measured. A new array architecture having a connection gate is designed for the 3D stacked bit-line NAND flash memory application.
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Physical Sciences and Engineering
Engineering
Electrical and Electronic Engineering
Authors
Jang-Gn Yun, Jong Duk Lee, Byung-Gook Park,