Data retention under gate stress on a NVM array

This work is devoted to an original experimental method based on a classical data retention performed under a continuous gate stress. The method proposed here allows to discriminate the possible leakage paths in a non-volatile electrical memory array, but it is also the first step to the research of an equivalence between electrical stress and thermal stress. A specific array called Cell Array Structure Test (CAST) is used as a fast statistical characterization tool. The measurements are treated by a fast calculation method, allowing to extract the number of marginal cells. One of the major result of this study, apart from demonstrating the relevance of our experimental tool, lies in the demonstration and the confirmation that the charges leakage occurs mainly through tunnel oxide. This method has been applied on an EEPROM CAST – 0.09 μm technology node, but it is extendable to a lot of devices and architectures.

► We develop an original method of gate stress during data retention. ► We identify the tunnel oxide leakage path for charge losses from the floating gate. ► We extract the number of extrinsic cells in a large NVM array.