On-chip inductor above dummy metal patterns

This work characterizes the on-chip inductor above dummy metals in CMOS technology. Since the dummy pattern influences the sheet resistance in chemical–mechanical planarization (CMP) process strongly [Schindler G, Steinlesberger G, Engelhardt M, Steinhögl W. Electrical characterization of copper interconnects with end-of-roadmap feature sizes. Solid-State Electron 2003;47:1233–36; Smith S, Walton AJ, Ross AWS, Bodammer GKH, Stevenson JTM. Evaluation of sheet resistance and electrical line width measurement techniques for copper damascene interconnect. IEEE Trans Semicond Manuf 2002;15:214–22.], three test structures are fabricated to compare the inductor performances in this paper. The measurements show that the Q value degrades 15.3% and self-resonance frequency decreases 9.5% in device with dummy metal pattern. Accordingly, an equivalent circuit is proposed to analyze this behavior, the results show that the insulator capacitor plays a key role in performance degradation. Result of this study quantifies the effect of on-chip inductor above dummy pattern.