Design and optimization of the SOI field effect diode (FED) for ESD protection

A thorough investigation is carried out by numerical simulations of the field effect diode (FED) with the aim to explore its potential for ESD protection applications in silicon on insulator (SOI) technologies. It is shown that the carrier lifetime value has an important impact on the device operation. By careful sizing and doping, FED devices with reasonable breakdown voltage values can be achieved but at rather high gate voltage values. Better results are achieved by modifying the doping profile to resemble a PNPN structure with two gates.