Investigation of 65 nm CMOS transistor local variation using a FET array

CMOS FET local variation has been investigated using a new FET array structure. Key findings include four aspects. (1) At deep sub-micron technology node, local variation is significantly higher than global variation. Only 5–10% of total variation is a result of global variation. (2) Sample size affects point estimate of local variation. Sample size error can account for a significant portion of the fluctuation in the point estimate of local variation. (3) Well proximity effect (WPE) has a small impact on Vt local variation. Its impact on local variation of drive current is more significant. (4) Local variation reduces with temperature. The magnitude of NMOS Vt local variation reduction is more pronounced than PMOS. These results form a solid foundation to accurately model MOSFET local variation.