Modeling and optimization of series resistance of planar MIM capacitors

Integrated circuits for analog and telecom applications require metal insulator metal (MIM) capacitors with not only a high capacitance value (typically 5 nF/mm2), but also a low series resistance Rs. The optimization of this latter parameter is investigated in this paper, by means of a simple analytical model, taking into account both the impact of material parameters and device architectures, suggesting possible strategies for Rs minimization. Such a model is also suitable for MIM circuit simulation, and can be also extended to other devices, such as to the gate series resistance modeling of RF MOSFET. Results are in good agreement with numerical simulations and HF measurements, performed on state of the art planar MIM devices. Moreover, discussion on via placement to access the top electrode has been held, in order to optimize the series resistance of the capacitor.