Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
749640 | Solid-State Electronics | 2006 | 7 Pages |
Abstract
This paper presents a compact and semi-empirical model for a four-terminal (independent top and bottom gates) junction field-effect transistor (JFET). The model describes the steady-state characteristics for all bias conditions with a unified equation. Moreover, the model provides a high degree of accuracy and continuity for the different operation regions, a critical factor for robust analog circuit simulations. Capacitance modeling is also included to describe the JFET small-signal behavior. The model has been implemented in Cadence framework via Verilog-A and compared with data measured from JFETs used at Texas Instruments.
Related Topics
Physical Sciences and Engineering
Engineering
Electrical and Electronic Engineering
Authors
Hao Ding, Juin J. Liou, Keith Green, Claude R. Cirba,