Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
749665 | Solid-State Electronics | 2007 | 7 Pages |
Abstract
Based on the fully two-dimensional (2D) Poisson’s solution in both silicon film and insulator layer, a compact and analytical threshold voltage model, which accounts for the fringing field effect of the short channel symmetrical double-gate (SDG) MOSFETs, has been developed. Exploiting the new model, a concerned analysis combining FIBL-enhanced short-channel effects and high-k gate dielectrics assess their overall impact on SDG MOSFET’s scaling. It is found that for the same equivalent oxide thickness, the gate insulator with high-k dielectric constant which keeps a great characteristic length allows less design space than SiO2 to sustain the same FIBL induced threshold voltage degradation.
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Authors
T.K. Chiang, M.L. Chen,