A numerical study of field plate configurations in RF SOI LDMOS transistors

The effect of the source field plate architecture on the static and dynamic electrical performances of SOI LDMOS transistors for RF applications is analysed in this paper. Three architectures are envisaged: source field plate SFP, extended gate field plate and independently biased field plate. Moreover, two different drift diffusion profiles are considered: shallow SDD and deep doped DDD diffusion. The resultant drift region is analytically modelled and the impact of geometrical and technological parameters on the transconductance value is determined by means of numerical simulation techniques. Finally, the dependence of the LDMOS capacitances on the field plate configuration is also studied. Simulation results show the trade-off between reliability and transconductance in each field plate configuration. In spite of the power efficiency improvement, the field plate biasing can significantly degrade the SOI LDMOS performances due to hot-carrier and self-heating effects. On the contrary, the SFP configuration leads to an enhanced reliability at the cost of the on-state resistance increase. The SFP structure with deep doped drift (DDD) diffusion provides the best performances in terms of cut-off frequency and self-heating degradation.