Parasitic capacitance removal of sub-100 nm p-MOSFETs using capacitance–voltage measurements

Capacitance–voltage measurements are performed on sub-100 nm high-k/metal gate p-MOSFETs to extract the intrinsic capacitance per gate length. This is then repeated on simulated devices using finite element modeling to compare to the experimental results. The intrinsic channel capacitance for the simulated devices is isolated from the parasitic capacitance, allowing for the comparison of analytic models of parasitic capacitances to the simulation.

► C–V measurements on various gate length high-k/metal gate sub-100 nm p-MOSFETs. ► Intrinsic channel capacitance is removed. ► Method is repeated on devices simulated using Sentaurus for comparison to experimental device. ► Parasitic capacitance behavior is discussed. ► Simulated parasitic terms are compared to analytical models.