Investigation of scalability of In0.7Ga0.3As quantum well field effect transistor (QWFET) architecture for logic applications

In this paper, the scalability of In0.7Ga0.3As QWFET is investigated using two-dimensional numerical drift–diffusion simulation. Numerical drift–diffusion simulations were calibrated using experimental results on short-channel In0.7Ga0.3As QWFETs [7] to include the effects of velocity overshoot. Logic figures of merit (sub-threshold slope, saturated threshold voltage, drain induced barrier lowering, ION/IOFF ratio over a specified gate swing, effective injection velocity and intrinsic switching delay) extracted from the numerical simulations are in excellent agreement with the experimental data. Three alternate QWFET device architectures are proposed and thoroughly investigated for 15 nm node and beyond logic applications. Amongst them, double-gate In0.7Ga0.3As QWFET shows the best scalability in terms of logic figures of merit, thus making it an ideal candidate for the design and demonstration of the ultimate scaled transistor.

► The scalability of In0.7Ga0.3As QWFETs for 15 nm node and beyond logic applications is investigated. ► Excellent agreements between experimental measurements and drift–diffusion simulation results have been demonstrated. ► The significance of source side injection velocity is emphasized for short channel length III-V QWFETs operating in quasi ballistic mode. ► Of QWFET architectures investigated, double gate QWFET achieves the best logic figure of merit from both transport and scalability standpoint.