Three-dimensional analytic modelling of front and back gate threshold voltages for small geometry fully depleted SOI MOSFET’s

New 3-D analytical models of front and back gate threshold voltages for fully depleted SOI MOSFET’s have been described here. The present models take into account the contributions of all the three paths of conduction such as front gate oxide-silicon, back gate oxide-silicon and side wall oxide-silicon interfaces in mesa isolated structure of such MOSFET’s. In order to do this, 3-D Poisson’s equation has been solved analytically with suitable boundary conditions to obtain an explicit expression of electrostatic potential within fully depleted SOI film with uniform doping concentration. With the help of this expression, the compact and closed form formulae of front and back gate threshold voltages under various conditions have been established. In addition to this, the closed form expressions of biasing counterparts of front and back threshold voltages i.e. respective back and front gate biases have also been reported in order to decide required operational modes of both interfaces of the device. The calculated results of the threshold voltages have been validated with available numerical data.

► New 3-D front (back) gate threshold voltage models of FD-SOI MOSFETs are reported. ► Models solve 3-D Poisson’s equation using Green’s function as a tool. ► 3-D threshold voltage models include side wall, source/drain and back gate effects. ► Front and back gate charge coupling is incorporated in both the threshold voltages. ► Compact models of threshold voltages are amenable to circuit CAD tool.