| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 753104 | Solid-State Electronics | 2011 | 7 Pages |
Abstract
⺠Effect of process-induced negative charges at the gate edges on MOSFETs performance. ⺠NCs at the gate edges can degrade subthreshold behavior and analog FoM of MOSFET. ⺠Enhanced Gmmax and apparent better SCE control can be due to NCs at the gate edges. ⺠Such behavior may appear in any advanced technology employing novel gate stacks. ⺠Complete set of device characteristics is required for a fair technology assessment.
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Electrical and Electronic Engineering
Authors
V. Kilchytska, J. Alvarado, N. Collaert, R. Rooyackers, S. Put, E. Simoen, C. Claeys, D. Flandre,