Gate-all-around technology: Taking advantage of ballistic transport?

This work presents an experimental study in order to evaluate the quality of transport in the most advanced state-of-the-art gate-all-around devices in term of performances. Experiments have been done on silicon channel devices with metal/high-k gate all-round stack at aggressive dimensions (L × W × TSi = 25nm × 20 nm × 10nm). We deeply investigated the mobility and the limiting velocity in order to evaluate the possible occurrence of ballisticity. Interest of the gate-all-around in terms of effective current and parasitic capacitance has then been studied in the scope of elementary circuit perspectives.