Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
753338 | Solid-State Electronics | 2009 | 6 Pages |
Abstract
Enclosed-layout transistors fabricated in standard CMOS processes are known to offer a natural robustness against radiation effects, a characteristic which is boosted in submicron technologies due to the reduction of the oxide thickness. In this paper, a thorough analytical I–V model of short-channel polygonal enclosed-layout transistors is proposed, addressing the issues of drain-induced barrier lowering and threshold voltage roll-off due to short-channel effects. Experimental data is reported, showing good agreement with the theoretical model.
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Authors
P. López, J. Hauer, B. Blanco-Filgueira, D. Cabello,