CMOS 6-T SRAM cell design subject to “atomistic” fluctuations

Intrinsic parameter fluctuations adversely affect SRAM cell stability, and will become one of the major factors limiting future CMOS 6-T SRAM scaling. In this work, using the driveability ratio and cell ratio parameters, and employing ‘Write Assist’ technology, we present a compromise design methodology which can balance WNM and SNM performance, improving CMOS 6-T SRAM scalability in the decananometer regime. The feasibility of the approach is demonstrated through detailed statistical SRAM simulations using models calibrated against MOSFETs with physical gate length of 35 nm.