| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 753493 | Solid-State Electronics | 2007 | 7 Pages |
The fully-depleted version of the SOI four-gate transistor (G4-FET) is introduced and its characteristics are systematically investigated. It is shown that the thinning-down of the silicon film promotes vertical coupling between the front and the back gates while mitigating the horizontal coupling between the lateral gates. As a consequence the direct influence of the lateral junction-gates on the body potential distribution is reduced. However, by biasing the back interface in inversion the junction-gates can indirectly modulate the body potential. This provides a very efficient control of the front-channel conduction parameters – such as threshold voltage, subthreshold swing and transconductance – by the junction-gates regardless the device width. The experimental results are clarified by 3-D device simulations and analytical modelling.
