Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
7939581 | Superlattices and Microstructures | 2017 | 9 Pages |
Abstract
This paper investigates the performance of 6Â T SRAM cell using high-K gate dielectric based junctionless silicon nanotube FET (JLSiNTFET). It is observed that the use of high-K gate dielectric enhances the delay performance of the JLSiNTFET based 6Â T SRAM cell. Read access time (RAT) and write access time (WAT) improves by â¼18% and â¼20% when TiO2 is used as gate dielectric instead of SiO2. The hold, read, and write SNMs (static noise margin) of the 6Â T SRAM cell also improves marginally by the use of high-K gate dielectric. Furthermore, it is also observed that the improvement in hold SNM (HSNM), read SNM (RSNM), and write SNM (WSNM) can be boosted by using higher interfacial layer thickness (TI). However, the improvement in read access times (RAT) & write access time (WAT) degrades at higher TI. Thus, high-K gate dielectrics with high interfacial layer thickness are more suitable for JLSiNT-FET based 6Â T SRAM cell.
Keywords
Related Topics
Physical Sciences and Engineering
Materials Science
Electronic, Optical and Magnetic Materials
Authors
Shubham Tayal, Ashutosh Nandi,