Effect of air spacer on analog performance of underlap tri-gate FinFET

In this work, a symmetric underlap tri-gate FinFET is studied to analyze the impact of Air-spacer, on the analog performance of the device. With the use of air-spacer, the parasitic capacitances are reduced which improves the overall capacitances of the device. Further, the capacitance of the device is reduced by optimizing the spacer length. This in-turn improves the analog figure-of-merit (FOM) of the devices. Hence, the device is useful for the high-frequency applications. The FOM are extracted at 10 μA/μm current level targeting low power applications. We observe a marginal change in the intrinsic gain of different spacer dielectric (Si3N4, SiO2 and air) based underlap TG-FinFETs. Whereas the frequencies like fT, fMAX of air spacer based underlap TG-FinFET is enhanced by 35% and 42.6% respectively as compared to Si3N4 spacer based underlap TG-FinFET. Furthermore, we have also specified the useful region of operation of air spacer based TG-FinFET in terms of gain bandwidth product (GBWP).