Article ID Journal Published Year Pages File Type
7941000 Superlattices and Microstructures 2017 15 Pages PDF
Abstract
Various limitations, such as gate leakage through hot carrier tunnelling, parasitic resistance and capacitance, Drain Induced Barrier Lowering (DIBL), subthreshold slope (SS), and threshold voltage roll-off are present due to size reduction. Improvements in transistor speed and performance while, reducing the device dimensions is possible using the concept of Multiple-gate Field Effect phenomenon. Temperature dependency in thin fin transistor has been systematically studied with respect to the dependence on the fin width, fin height, and gate length. In this paper the performance of miniaturized Fin-FET structure is optimized. Also, temperature (300K, 400K and 500K) dependent performances on DIBL, SS and threshold voltage are observed and optimized.
Related Topics
Physical Sciences and Engineering Materials Science Electronic, Optical and Magnetic Materials
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