A novel high performance nano-scale MOSFET by inserting Si3N4 layer in the channel

In this paper a novel feature of a nano-scale SOI-MOSFET is presented. The goal of the proposed Si3N4 Layer SOI-MOSFET (SL-SOI) is inserting a Si3N4 layer in the channel region. This layer in the channel region which has different band gap than silicon causes uniform electric field. So, hot carrier effect and gate current are controlled sufficiently. Moreover, Si3N4 layer in the channel is extended in the buried oxide to reduce the lattice temperature, and sub-threshold slope. The proposed structure is simulated with two-dimensional ATLAS simulator and compared with conventional SOI-MOSFET. The results show that the new device has a high performance which expands nano-scale MOSFET applications in high temperature.