| Article ID | Journal | Published Year | Pages | File Type |
|---|---|---|---|---|
| 7942652 | Superlattices and Microstructures | 2014 | 12 Pages |
Abstract
In this paper, we focus on the VGE overshoot phenomenon of the 1.2Â kV Injection Enhanced Gate Transistor (IEGT) caused by the reverse gate capacitance displacement current during the turn on operation. It is found that the VGE overshoot is in proportion to the ratio between the surface current (i.e. the current flow through the surface of the device under the trench gate, IS) and the collector current IC. The formation mechanism of the surface current and its impact on the gate voltage overshoot have been analyzed in detail and verified by numerical simulation. According to the analysis, a design method is proposed to reduce the IS/IC. As a consequence, the VGE overshoot has been reduced. Finally, a design case employing the separated floating p-layer is presented to verify the design method and shows the small VGE overshoot.
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Authors
Zhuo Yang, Xiaoyuan Li, Jing Zhu, Weifeng Sun,