Optimization of fabrication process of high-efficiency and low-cost crystalline silicon solar cell for industrial applications

The process conditions for a high-efficiency and low cost crystalline silicon solar cell were optimized. Novel approaches such as wafer cleaning and saw -damage removal using 0.5 wt% of 2,4,6-trichloro-1,3,5-triazine, silicon surface texturing with optimized pyramid heights (∼5 μm), and a third step of drive-in after phosphosilicate glass (PSG) removal followed by oxide removal were investigated. A simple method of chemical etching adopted for edge isolation was optimized with edge etching of 5–10 μm, without any penetration of chemicals between the stacked wafers. The conversion efficiency, open-circuit voltage, short-circuit current, and fill factor of the cell fabricated with the optimized process were a maximum of 17.12%, 618.4 mV, 5.32 A, and 77% under AM1.5 conditions, respectively.