Fabrication of ultra-thin strained silicon on insulator by He implantation and ion cut techniques and characterization

8-inch strained silicon on insulator (sSOI) wafer with 13 nm strained Si top layer has been obtained using He implantation, wafer bonding, layer transfer and selective etching techniques. Different from the conventional graded buffer layer with considerable thickness, the relaxed SiGe virtual substrate, which provides the lattice template for strained Si epitaxy, is achieved by the process combining He implantation and rapid thermal annealing. The strain relaxation in SiGe virtual substrate and the strain transfer from SiGe virtual substrate to the strained Si have been examined by X-ray diffraction reciprocal space mapping. The final 8-inch sSOI wafer is characterized for stress uniformity, thickness uniformity, crystalline quality, defect density and surface roughness using a variety of techniques and found to be in acceptable quality for the application in advanced device fabrication.