Level shifting circuit for hybrid superconductor-to-semiconductor interface

Memory circuits based on superconductivity electronics by the presence of very high speed of switching and extremely low consumption of power have no suitable density. For this purpose, the hybrid circuit of superconductor-semiconductor was proposed. The main idea of this circuit is concentration on using the advantages of each one of two technologies. In construction of memory circuits, designing an interface hybrid circuit of superconductor-semiconductor is considered as a big challenge, because this circuit should reach very weak signals of SFQ in output of circuit based on superconductor technology with low delay time of issue to suitable levels for applying to semiconductor circuit. Our proposed circuit is an amplifier including two stages. In the first stage, we use a memory circuit with Josephson junction as the name of Super Stack including Suzuki Stack series. This circuit changes 6 mV input to a few tens mV and we lower voltage level towards similar circuits by declining the number of Josephson junctions in each Suzuki Stack. The second stage of a circuit is latch comparator in semiconductor technology that receives its input from the output of first stage and reaches it to the limit of Volt level. In the first stage two Suzuki stacks were employed producing a 60 mV output with a propagation delay of 23 ps which represents a 51% improvement in speed compared with other topologies reported in the literature with similar output amplitudes. In the second stage, 16 nm graphene nano-ribbon transistors MOS-GNRFETs were used and the results were compared with those obtained based on CMOS 16 nm LP and CMOS HP transistors. Simulations indicated that the power delay product (PDP) is lower using graphene nano-ribbon transistors as compared with 16 nm CMOS LP and HP transistors by 54% and 79%, respectively. Furthermore, power consumption was lower for the topology employing MOS-GNRFETs as compared with those using 16 nm CMOS LP and HP devices by 47.2% and 78%, respectively. The speed performance is also discussed.