FPGA implementation of digital constant fraction algorithm with fractional delay for optimal time resolution

In a recent development of a fully digital spectrometer for time differential perturbed angular correlations a true constant fraction trigger (CFT) algorithm was implemented that, however, allowed for integer delays, i.e. integer multiples of the sampling interval, only. With a sampling rate of 1 GS/s and BaF2 scintillators this turned out to be insufficient. Here, we present an extension of the algorithm to fractional delays implemented in field programmable gate arrays (FPGAs). Furthermore, we derive a criterion for the delay for optimum timing based on the steepest slope of the CFT signal. Experimental data are given for LaBr3(Ce) scintillators and 511 keV-511 keV prompt coincidences that corroborate the theoretical result.