Design of Low Bandwidth Peripherals Using High Performance Bus Architecture

System on-chip (SOC) communication has a significant impact on system performance, power dissipation and time to market. System designers, as well as the researchers community focuses on low power dissipation. A reliable on-chip communication standard is a must in any SOC. The AMBA 2.0 APB is a peripheral bus standard for low bandwidth peripheral. In this paper, we present the design of APB controller which handles the transactions between the master and peripheral devices. The final design which integrates the peripheral devices with the APB controller and simulated.