Efficient Carry Select Adder Design for FPGA Implementation

Digital adder with optimum area and speed is one of the important areas of research in VLSI system design. This paper discusses about the efficient implementation of parallel adder with optimized area and propagation delay for FPGA applications. Our approach uses carry select adder configuration and parallel adder approach for the implementation of fast adder. There are different choices for implementing carry select adder. We compare some of these methods and choose the one appropriate for FPGA implementation. Two different approaches for implementing linear carry select adder using Kogge Stone configuration are discussed here and compared in terms of area and speed. Both approaches are implemented on an FPGA and the performance is compared. Simulation results are used to verify the theory.