Low Power Pipelined Dwt-Idwt Architecture for Ofdm System on Fpga

OFDM systems are widely used in most of the wireless communication systems. OFDM achieves better bandwidth efficiency and data rate. FFT module in OFDM system is being replaced with DWT to reduce complexities in hardware implementation. In this paper, we propose a modified Distributive Arithmetic (DA) based DWT architecture for OFDM system. The proposed module is implemented on FPGA and its performances are compared with parallel and pipelined DA DWT architecture. The proposed DWT logic operates at a maximum frequency of 378MHz and consumes power less than 26 mW. The memory size is reduced from 256 bytes to 16 bytes thus saving large storage space on FPGA. Functional verification of the developed system is carried out using modelsim. Simulink models for the OFDM unit are developed and performances are estimated.