Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
865302 | Tsinghua Science & Technology | 2011 | 7 Pages |
Abstract
Divide-and-conquer methods for FPGA placement algorithms including partition-based and cluster-based algorithms have shown the importance of good quality-runtime trade-off. This paper describes a cluster-based FPGA placement algorithm targeted to a new commercial hierarchical FPGA device. The algorithm is based on a Markov clustering algorithm that defines a sequence of stochastic matrices operating on a generating matrix from the input FPGA circuit netlist. The core of the algorithm tightly couples a Markov clustering process with a multilevel placement process. Tests show its excellent adaptability to hierarchical FPGAs. The average wirelength results produced by the algorithm are 22.3% shorter than the results produced by the current hierarchical FPGA placer.
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Authors
Dai (æ´æ), Zhou (å¨å¼º), Bian (边计年),