24-bit Low-Power Low-Cost Digital Audio Sigma-Delta DAC

This paper describes a low-power low-cost 24-bit Σ-Δ digital-to-analog converter (DAC) for portable digital-audio applications. The interpolation filter uses a no-multiplier scheme to implement the arithmetic units and reading-writing common storage scheme for the delay-line to significantly reduce the die area. A 15-level quantizer, third-order, single-stage Σ-Δ modulator is employed to reduce the passband quantization noise, relax the out-of-band filtering requirements, and enhance immunity to clock jitter. A data weighted averaging algorithm is used to mitigate the nonlinearity caused by capacitor mismatch. A direct charge transfer switched-capacitor low-pass filter (DCT-SC LPF) is used to reconstruct the analog signal to reduce the kT/C noise and capacitor mismatch effect with a small increase of the power dissipation. The chip was fabricated in the SMIC 0.13 μm 1P5M CMOS process. The cell area of the digital part is 0.056 mm2 and the total area of the analog part is 0.34 mm2. The supply voltage is 1.2 V for the digital circuit and 3.3 V for the analog circuit. The power consumption of the analog part is 3.5 mW. The audio DAC achieves a 100 dB dynamic range and an 84 dB peak signal-to-noise-plus-distortion ratio over a 20 kHz passband. The results show that these performances are good enough for high quality portable audio applications.