Vertical SiGe-based silicon-on-nothing (SON) technology for sub-30Â nm MOS devices

A new device concept is introduced, the vertical silicon-on-nothing field-effect transistor. The “nothing” region is obtained by the selective removal of an epitaxial SiGe layer. Both the channel length and the gate width are determined by epitaxial deposition, and are not limited by lithography. Since there is “nothing” under the gate, the device should be suitable for operation in high-radiation environments. By estimating the gate overlap, we predict an ultimate FT of 100 GHz. Initial devices in bridge, trench, and cantilever configurations are shown. In the first device fabrication, the choice of SiO2 for the gate dielectric resulted in the formation of parasitic transistors that dominated the electrical performance.