Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
9699154 | Materials Science in Semiconductor Processing | 2005 | 6 Pages |
Abstract
We present simplifications to the strained Si wafer fabrication process that simultaneously improve wafer quality and process throughput. This process includes a short duration high-temperature bake and strained Si deposition directly on a planarized SiGe virtual substrate, without an intermediate low-temperature SiGe regrowth step between the planarized interface and the strained Si layer. By depositing the strained Si film directly on the planarized SiGe virtual substrate, we have developed a strained Si wafer manufacturing process featuring extremely low surface roughness (<0.2 nm RMS for 40Ã40 μm2 scan atomic force microscopy scans, <0.1 nm RMS for 1Ã1 μm2 scan atomic force microscopy scans), excellent interface abruptness, and the ability to achieve regrowth process cycle time better than 5 min/wafer.
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Authors
Christopher Leitz, Vicky Yang, Mark Carroll, Thomas Langdo, Richard Westhoff, Christopher Vineis, Mayank Bulsara,