Article ID | Journal | Published Year | Pages | File Type |
---|---|---|---|---|
9699179 | Materials Science in Semiconductor Processing | 2005 | 10 Pages |
Abstract
We have studied (1Â 1Â 0)-surface strained-SOI n- and p-MOSFETs on (1Â 1Â 0)-surface relaxed Si0.75Ge0.25-on-insulator structures, applying the Ge condensation technique to SiGe layers grown on (1Â 1Â 0)-surface SOI wafers. We have demonstrated that the electron and the hole mobility enhancement of (1Â 1Â 0)-surface strained-SOI devices amounts to 23% and 50%, respectively, against the mobilities of (1Â 1Â 0)-surface unstrained MOSFETs. As a result, the electron and the hole mobility ratios of (1Â 1Â 0)-surface strained-SOI MOSFETs to the universal mobility of (1Â 0Â 0)-surface bulk-MOSFETs increase up to 81% and 203%, respectively. Therefore, the current drivability unbalance between n- and p-MOS can be reduced. Moreover, both the electron and the hole mobilities of the (1Â 1Â 0)-surface strained-SOIs strongly depend on the drain current flow direction, which is explained by anisotropic effective mass characteristics of the carriers. We have also introduced a simple model for electric field dependence of hole mobility of (1Â 1Â 0)-surface strained- and unstrained-MOSFETs. (1Â 1Â 0)-surface strained-SOI technology is also the candidate for higher speed scaled CMOS, optimizing the current flow directions of n- and p-MOS.
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Authors
T. Mizuno, N. Sugiyama, T. Tezuka, Y. Moriyama, S. Nakaharai, T. Maeda, S. Takagi,