Strained-Si n-MOS surface-channel and buried Si0.7Ge0.3 compressively-strained p-MOS fabricated in a 0.25 μm heterostructure CMOS process

A 0.25 μm complimentary metal oxide semiconductor (CMOS) process has been used to fabricate surface channel strained-Si n-MOS devices and buried, compressively-strained-Si0.7Ge0.3 channel p-MOS. Enhancements in performance of on-current, transconductance and mobility over bulk, relaxed Si CMOS devices are demonstrated for both n- and p-MOS devices for all gate lengths fabricated from 0.1 up to 10 μm. The performance is compared to surface channel strained-Si CMOS which is superior to the buried channel results. Possible reasons are discussed.