Advanced 65Â nm CMOS devices fabricated using ultra-low energy plasma doping

For leading edge CMOS and DRAM technologies, plasma doping (PLAD) offers several unique advantages over conventional beamline implantation. For ultra-low energy source and drain extensions (SDE), source drain contact and high dose poly doping implants PLAD delivers 2-5× higher throughput compared to beamline implanters. In this work we demonstrate process performance and process integration benefits enabled by plasma doping for advanced 65 nm CMOS devices. Specifically, p+/n ultra-shallow junctions formed with BF3 plasma doping have superior Xj/Rs characteristics to beamline implants and yield up to 30% lower Rs for 20 nm Xj while using standard spike anneal with ramp-up rate of 75 °C/s. These results indicate that PLAD could extend applicability of standard spike anneal by at least one technology node past 65 nm. A CMOS split lot has been run to investigate process integration advantages unique to plasma doping and to determine CMOS device characteristics. Device data measured on 65 nm transistors fabricated with offset spacers indicate that devices with SDE formed by plasma doping have superior Vt roll-off characteristics arguably due to improved lateral gate-overlap of PLAD SDE junctions. Furthermore, offset spacers could be eliminated in 65 nm devices with PLAD SDE implants while still achieving Vt roll-off and Ion−Ioff performance at least equivalent to control devices with offset spacers and SDE formed by beamline implantation. Thus, another advantage of PLAD is simplified 65 nm CMOS manufacturing process flow due to elimination of offset spacers. Finally, we present process transfer from beamline implants to PLAD for several applications, including SDE and gate poly doping with very high productivity.