Characterization of polysilicon thin-film transistors with asymmetric source/drain implantation

The effect of asymmetry tilt angle ion implantation on polysilicon thin-film transistors (TFTs) device characteristics are investigated. This asymmetric source/drain (S/D) TFTs structure exhibits low leakage current and suppressed kink effect due to the relief of higher electric field near the drain junction side. It is shown that the optimal implantation tilt angle is 30° in our annealing condition. And the anomalous off-state current is more than two orders of magnitude lower than that of the conventional TFTs. By well controlled the LDD region, this structure can act as a conventional structure in the on-state and the turn-on current will not be degraded. Besides, the device under severe hot carrier bias stress shows better hot carrier endurance.