Optimizing SMT processors for IP-packet processing

Simultaneous multithreading (SMT) processors support multiple active concurrent hardware threads in order to share processor resources such as functional units and memory. This thread-level-parallelism (TLP) can be exploited in form of packet-level-parallelisms required in packet processing devices called network processors. In this paper, we propose hardware queues for scheduling process threads which causes 25% improvement in the throughput of IP-lookup threads. To optimize our target SMT network processor, we used IP-hashing to improve the overall packet throughput and reduce latency. We also propose some load-balancing mechanisms in the level of process threads. These optimizations are evaluated using our simulation environment called NPSMT, which simulates a typical SMT network processor, a network controller and a packet generator. In addition to fast and memory sensitive IP-lookup threads, we also used slow process sensitive MD5 threads in our scenarios. Considering the effect of different parameters of the processor and network controller, we discuss the performance achieved for MD5 and IP-lookup program (Netbench benchmarks) under different workloads. Our results show that IP-lookup memory sensitivity is spread into all other running threads (MD5) and the whole system is much more sensitive to memory speed rather than other processor parameters such as the number of ALUs and the ILP capacity.