Memory reference caching for activity reduction on address buses

Switching activity on I/O pins of a chip is a measurable contributor to the total energy consumption of the chip. In this work, we present an encoding mechanism that reduces switching activity of external address buses by combining a memory reference caching mechanism with Unit Distance Redundant Codes (UDRC). UDRC are codes that guarantee a Hamming distance of at most one between any pair of encoded symbols. Memory reference caching exploits the fact that memory references are likely to be made up of an interleaved set of sequential streams. Memory reference caching isolates these, otherwise interleaved, streams and limits the communication to an UDRC encoded message that identifies the particular stream, at the cost of at most a single bit-transition. Experiments with 18 embedded system as well as general applications show an average of 58% reduction in switching activity, with the best and worse cases being 86 and 36%, respectively. The maximum performance penalty (i.e. critical-path delay) for a proposed encoder and decoder is 16 and 14 gates, respectively. The area overhead for a proposed encoder and decoder is equivalent to 2033 and 1858 2-input NAND gates, respectively.