An infrastructure for designing custom embedded wide counterflow pipelines

Application-specific instruction set processor (ASIP) design is a promising approach for meeting the performance and cost goals of embedded systems. We have developed a new microarchitecture, called a wide counterflow pipeline (WCFP), for automatically constructing ASIPs. Our ASIP synthesis technique uses software pipelining and design-space exploration to generate a custom WCFP and instruction set for an embedded application. This paper describes an innovative methodology and framework for WCFP synthesis and the lessons learned from designing and building the infrastructure. These lessons can be applied to other automated design tools for application-specific processors. The framework includes a user-supplied design database, intermediate representations for pipeline organization and custom instruction set architecture, and a reconfigurable simulator and performance analysis tool. The paper describes how the requirements and needs of automatic architectural design for WCFPs influenced the synthesis methodology and framework. To demonstrate the framework, we show its usefulness in refining the organization of custom WCFPs to better match the execution behavior of an application.